For the Inventor, By the Inventor

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Boston, MA, United States of America

Slt Logic, LLC

Calculating rank

USPTO Granted Patents = 26

% Expired Patents = 84.6

Forward Citations = 2,407

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23 inventors (with patents filed for the assignee):

Scott A Sarkinen (8 out of 12 patents)

Van L Jacobson (6 out of 42 patents)

Rodolfo A Santiago (6 out of 6 patents)

4. Alan Fiedler (4 out of 18 patents)

5. Bob Felderman (4 out of 6 patents)

6. Glenn A Buskirk (4 out of 4 patents)

7. Hemant Vrajlal Trivedi (4 out of 6 patents)

8. Viswa Nath Sharma (4 out of 17 patents)

9. Martin F Eberhard (4 out of 45 patents)

10. William Chu (2 out of 6 patents)

11. Gregg T Sarkinen (2 out of 3 patents)

12. Jeremy B Paatela (2 out of 2 patents)

13. Archibald L Cobbs (2 out of 4 patents)

14. Scott Allen Davidson (2 out of 11 patents)

15. David Bruce Lentz (1 out of 2 patents)

Core Competencies:

Data Flows

Multi-Protocol

Real-Time Classification

High-Speed Sampling

Secure Connection

Chassis Design

Programmable Scheduler

Queuing Method

Network Architecture

Input Threshold Adjustment

Flow Policing

Multi-Service

26 patents: Sort by Forward Citations

1. 7978606 - System and method for policing multiple data flows and multi-protocol data flows (2011-07-12),

2. 7835375 - Method and apparatus for providing multi-protocol, multi-stage, real-time frame classification (2010-11-16),

3. 7827442 - Shelf management controller with hardware/software implemented dual redundant configuration (2010-11-02),

4. 7822048 - System and method for policing multiple data flows and multi-protocol data flows (2010-10-26),

5. 7821790 - Modular chassis providing scalable mechanical, electrical and environmental functionality for MicroTCA and Advanced TCA boards (2010-10-26),

6. 7813460 - High-speed data sampler with input threshold adjustment (2010-10-12),

7. 7782873 - Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks (2010-08-24),

8. 7688853 - System and method for hierarchical policing of flows and subflows of a data stream (2010-03-30),

9. 7580495 - Mixer-based phase control (2009-08-25),

10. 7573967 - Input threshold adjustment in a synchronous data sampling circuit (2009-08-11),

11. 7539195 - System and method for providing transformation of multi-protocol packets in a data stream (2009-05-26),

12. 7453892 - System and method for policing multiple data flows and multi-protocol data flows (2008-11-18),

13. 7386619 - System and method for allocating communications to processors in a multiprocessor system (2008-06-10),

14. 7316017 - System and method for allocatiing communications to processors and rescheduling processes in a multiprocessor system (2008-01-01),

15. 7285996 - Delay-locked loop (2007-10-23),

Company Overview

Slt Logic, LLC is a Boston-based company specializing in advanced logic design and semiconductor technology. The organization focuses on developing innovative solutions that enhance performance and efficiency in electronic systems. With a strong emphasis on research and development, Slt Logic is dedicated to pushing the boundaries of technology in various domains, including integrated circuits and digital systems. Their expertise positions them as a key player in the evolving landscape of electronic engineering and design.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

26 Patents

#94 in Boston, MA

#776 in Massachusetts

#12,875 in US

#24,848 in the World

Boston, MA, United States of America

Slt Logic, LLC

Forward Citations = 2,407

23 inventors:

Scott A Sarkinen (8 out of 12 patents)

Van L Jacobson (6 out of 42 patents)

Rodolfo A Santiago (6 out of 6 patents)

4. Alan Fiedler (4 out of 18 patents)

5. Bob Felderman (4 out of 6 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Slt Logic, LLC. Retrieved from https://idiyas.com/company/slt-logic

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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