The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2007
Filed:
Sep. 30, 2005
Alan Fiedler, Niskayuna, NY (US);
Alan Fiedler, Niskayuna, NY (US);
SLT Logic, LLC, Boston, MA (US);
Abstract
A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the clock input signal. The delay line can be configured so that one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal. The feedback portion of the circuit can be configured to generate delay adjust signals based upon the phase offsets between pairs of clock signals. The delay adjust signals are fed back to the delay elements causing the reference input clock signal and the clock output signals to be phase-shifted apart equally about 360 degrees.