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Sunnyvale, CA, United States of America

Sequence Design, Inc.

USPTO Granted Patents = 28

Forward Citations = 831

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24 inventors (with patents filed for the assignee):

Robert G Mathews (8 out of 9 patents)

Adi Srinivasan (7 out of 26 patents)

Keh-Jeng Chang (6 out of 8 patents)

4. Gerald L Frenkil (5 out of 11 patents)

5. Glen Anderson (3 out of 12 patents)

6. Li-Fu Chang (3 out of 5 patents)

7. David L Allen (2 out of 10 patents)

8. Wei Ey Li (2 out of 68 patents)

9. Donald Vick Organ (2 out of 8 patents)

10. Aidan Rhys Dwyer (2 out of 2 patents)

11. Sean Patrick Dwyer (2 out of 2 patents)

12. Douglas Kaufman (2 out of 3 patents)

13. Hazem Almusa (2 out of 2 patents)

14. Vinay Srinivas (2 out of 2 patents)

15. Larry Ke (2 out of 2 patents)

28 patents: Sort by Forward Citations

1. 10115530 - Solar cell and methods of fabrication and use thereof (2018-10-30),

2. 9103567 - Photovoltaic array utilizing phyllotaxic architecture (2015-08-11),

3. 7590962 - Design method and architecture for power gate switch placement (2009-09-15),

4. 7509613 - Design method and architecture for power gate switch placement and interconnection using tapless libraries (2009-03-24),

5. 7323909 - Automatic extension of clock gating technique to fine-grained power gating (2008-01-29),

6. 7222318 - Circuit optimization for minimum path timing violations (2007-05-22),

7. 7222311 - Method and apparatus for interconnect-driven optimization of integrated circuit design (2007-05-22),

8. 7185300 - Vectorless instantaneous current estimation (2007-02-27),

9. 7117457 - Current scheduling system and method for optimizing multi-threshold CMOS designs (2006-10-03),

10. 7003741 - Method for determining load capacitance (2006-02-21),

11. 6901565 - RTL power analysis using gate-level cell power models (2005-05-31),

12. 6807660 - Vectorless instantaneous current estimation (2004-10-19),

13. 6754877 - Method for optimal driver selection (2004-06-22),

14. 6701507 - Method for determining a zero-skew buffer insertion point (2004-03-02),

15. 6701506 - Method for match delay buffer insertion (2004-03-02),

Sequence Design, Inc. is a leading electronic design automation (EDA) company based in California, USA. With over 25 years of experience, Sequence Design specializes in providing software tools and solutions for semiconductor companies to improve power, performance, and reliability of their integrated circuits. Their innovative products help engineers efficiently design and verify complex chips, optimizing their functionality while reducing time-to-market. Visit their website for more information about their cutting-edge EDA solutions and industry expertise.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 23 2025

28 Patents

#118 in Sunnyvale, CA

#2,765 in California

#11,595 in US

#22,555 in the World

Sunnyvale, CA, United States of America

Sequence Design, Inc.

Forward Citations = 831

24 inventors:

Robert G Mathews (8 out of 9 patents)

Adi Srinivasan (7 out of 26 patents)

Keh-Jeng Chang (6 out of 8 patents)

4. Gerald L Frenkil (5 out of 11 patents)

5. Glen Anderson (3 out of 12 patents)

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