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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Matrix Semiconductor, Inc.

USPTO Granted Patents = 145

% Expired Patents = 9.7

Forward Citations = 12,454

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57 inventors (with patents filed for the assignee):

goldMedal Roy E Scheuerlein (45 out of 270 patents)

silverMedal James Montague Cleeves (31 out of 146 patents)

bronzeMedal Mark G Johnson (25 out of 64 patents)

4.  Michael A Vyvoda (22 out of 30 patents)

5.  N Johan Knall (21 out of 41 patents)

6.  Christopher S Moore (21 out of 32 patents)

7.  Thomas H Lee (16 out of 72 patents)

8.  Andrew J Walker (15 out of 98 patents)

9.  Bendik Kleveland (14 out of 34 patents)

10.  Vivek Subramanian (13 out of 70 patents)

11.  Roger March (13 out of 17 patents)

12.  S Brad Herner (13 out of 95 patents)

13.  J James Tringali (12 out of 24 patents)

14.  Alper Ilkbahar (11 out of 52 patents)

15.  Derek Bosch (9 out of 20 patents)


Core Competencies:
Three-Dimensional Memory
High-Density Memory
Nonvolatile Memory
Memory Array
Write-Once Memory
Charge Storage
Transistor Layout
Integrated Circuit
Memory Device
Programming Method
Silicon Oxide
TFT Devices

145 patents:

1. 7177169 - Word line arrangement having multi-layer word line segments for three-dimensional memory array (2007-02-13),
2. 7149119 - System and method of controlling a three-dimensional memory (2006-12-12),
3. 7106652 - Word line arrangement having multi-layer word line segments for three-dimensional memory array (2006-09-12),
4. 7062602 - Method for reading data in a write-once memory device using a write-many file system (2006-06-13),
5. 7054219 - Transistor layout configuration for tight-pitched memory array lines (2006-05-30),
6. 7051251 - Method for storing data in a write-once memory array using a write-many file system (2006-05-23),
7. 7049678 - Diverse band gap energy level semiconductor device (2006-05-23),
8. 7026212 - Method for making high density nonvolatile memory (2006-04-11),
9. 7023739 - NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same (2006-04-04),
10. 7023260 - Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor (2006-04-04),
11. 7022572 - Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells (2006-04-04),
12. 7018878 - Metal structures for integrated circuits and methods for making the same (2006-03-28),
13. 7012299 - Storage layer optimization of a nonvolatile memory device (2006-03-14),
14. 7009275 - Method for making high density nonvolatile memory (2006-03-07),
15. 7005730 - Memory module having interconnected and stacked integrated circuits (2006-02-28),
Company Overview
Matrix Semiconductor, Inc., based in Santa Clara, California, specializes in the development of advanced three-dimensional memory technologies. The company focuses on creating high-density, nonvolatile memory solutions that enhance data storage capabilities. Its innovative approach includes the design of memory arrays and write-once memory systems, leveraging unique charge storage techniques and transistor layouts to optimize integrated circuit performance. Matrix Semiconductor is positioned at the forefront of memory technology, addressing the growing demands for efficient and scalable data storage solutions.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 20 2026

145 Patents

#30 in Santa Clara, CA

#596 in California

#2,705 in US

#5,627 in the World

Santa Clara, CA (US)
Santa Clara, CA, United States of America

Matrix Semiconductor, Inc.

Forward Citations = 12,454

57 inventors:

goldMedal Roy E Scheuerlein (45 out of 270 patents)

silverMedal James Montague Cleeves (31 out of 146 patents)

bronzeMedal Mark G Johnson (25 out of 64 patents)

4.  Michael A Vyvoda (22 out of 30 patents)

5.  N Johan Knall (21 out of 41 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Matrix Semiconductor, Inc.. Retrieved from https://idiyas.com/company/matrix-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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