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San Jose, CA, United States of America

Magma Design Automation, Inc.

USPTO Granted Patents = 44

% Expired Patents = 2.3

Trademarks = 2

Forward Citations = 1,696

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58 inventors (with patents filed for the assignee):

Arvind Srinivasan (8 out of 107 patents)

Premal Buch (6 out of 6 patents)

Lukas P P P Van Ginneken (6 out of 6 patents)

4. Haroon Chaudhri (5 out of 6 patents)

5. Hamid Savoj (5 out of 7 patents)

6. Timothy Michael Burks (4 out of 7 patents)

7. Samit Chaudhuri (3 out of 12 patents)

8. Yunjian (William) Jiang (3 out of 4 patents)

9. Mar Hershenson (3 out of 6 patents)

10. David M Colleran (3 out of 8 patents)

11. Emre Tuncer (2 out of 15 patents)

12. Alessandra Nardi (2 out of 9 patents)

13. Alfred Wong (2 out of 7 patents)

14. Manjit Borah (2 out of 3 patents)

15. Paul Kingsley Rodman (2 out of 22 patents)

Core Competencies:

Timing Analysis

Circuit Optimization

Power Distribution

Hierarchical Design

Crosstalk Noise

Clock Gating

Physical Synthesis

Routing Techniques

Statistical Analysis

VLSI Circuits

Design Constraints

Performance Estimation

44 patents: Sort by Forward Citations

1. 8006216 - Dynamic push for topological routing of semiconductor packages (2011-08-23),

2. 7992114 - Timing analysis using statistical on-chip variation (2011-08-02),

3. 7970590 - Parametric timing analysis (2011-06-28),

4. 7958476 - Method for multi-cycle path and false path clock gating (2011-06-07),

5. 7930673 - Method for automatic clock gating to save power (2011-04-19),

6. 7884649 - Selection of optimal clock gating elements (2011-02-08),

7. 7882461 - Method for optimized automatic clock gating (2011-02-01),

8. 7783996 - Optimization for circuit design (2010-08-24),

9. 7703050 - Optimization for circuit design (2010-04-20),

10. 7458049 - Aggregate sensitivity for statistical static timing analysis (2008-11-25),

11. 7458041 - Circuit optimization with posynomial function F having an exponent of a first design parameter (2008-11-25),

12. 7448003 - Signal flow driven circuit analysis and partitioning technique (2008-11-04),

13. 7434188 - Lithographically optimized placement tool (2008-10-07),

14. 7409658 - Methods and systems for mixed-mode physical synthesis in electronic design automation (2008-08-05),

15. 7353488 - Flow definition language for designing integrated circuit implementation flows (2008-04-01),

Company Overview

Magma Design Automation, Inc., based in San Jose, CA, specializes in advanced electronic design automation (EDA) solutions. The company focuses on enhancing integrated circuit performance through innovative technologies such as topological routing, statistical timing analysis, and circuit optimization. With expertise in physical synthesis and crosstalk noise reduction, Magma aims to streamline VLSI design processes, ensuring efficient and reliable electronic systems. Their solutions are pivotal for semiconductor companies seeking to improve design efficiency and product performance.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

44 Patents

#206 in San Jose, CA

#1,865 in California

#7,956 in US

#15,756 in the World

San Jose, CA, United States of America

Magma Design Automation, Inc.

Forward Citations = 1,696

58 inventors:

Arvind Srinivasan (8 out of 107 patents)

Premal Buch (6 out of 6 patents)

Lukas P P P Van Ginneken (6 out of 6 patents)

4. Haroon Chaudhri (5 out of 6 patents)

5. Hamid Savoj (5 out of 7 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Magma Design Automation, Inc.. Retrieved from https://idiyas.com/company/magma-design-automation

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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