The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
May. 28, 2008
Yunjian (William) Jiang, San Jose, CA (US);
Arvind Srinivasan, San Jose, CA (US);
Joy Banerjee, District Burdwan, IN;
Yinghua LI, San Jose, CA (US);
Partha Das, Kolkata, IN;
Samit Chaudhuri, Cupertino, CA (US);
Yunjian (William) Jiang, San Jose, CA (US);
Arvind Srinivasan, San Jose, CA (US);
Joy Banerjee, District Burdwan, IN;
Yinghua Li, San Jose, CA (US);
Partha Das, Kolkata, IN;
Samit Chaudhuri, Cupertino, CA (US);
Magma Design Automation, Inc., San Jose, CA (US);
Abstract
A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.