For the Inventor, By the Inventor

Enter assignee name

Sunnyvale, CA, United States of America

Artisan Components, Inc.

USPTO Granted Patents = 50

% Expired Patents = 6.0

Forward Citations = 908

Loading Chart...

Loading Chart...

23 inventors (with patents filed for the assignee):

Scott T Becker (32 out of 228 patents)

Dhrumil Gandhi (12 out of 24 patents)

Steve P Kornachuk (8 out of 8 patents)

4. Mark Templeton (4 out of 4 patents)

5. Daniel F LaBouve (3 out of 3 patents)

6. Ali A Iranmanesh (3 out of 49 patents)

7. Puneet Sawhney (2 out of 5 patents)

8. James C Mali (2 out of 2 patents)

9. Lyndon Charles Lim (2 out of 4 patents)

10. Michael J Brunolli (2 out of 43 patents)

11. Craig R Silver (2 out of 2 patents)

12. Brian Reed (1 out of 8 patents)

13. Sudhir S Moharir (1 out of 2 patents)

14. Chinh Luong Hoang (1 out of 10 patents)

15. Jayanth Thyamagundlam (1 out of 2 patents)

Core Competencies:

Built In Self Repair

Memory Column Redundancy

Integrated Circuits

Bitline Voltage Offsets

Leakage Current Reduction

Voltage Tolerant Circuit

Low Voltage Differential

Programmable ROM

Sense Amplifying Methods

High Speed Memory

Cell Architecture

Differential Signal Techniques

50 patents: Sort by Forward Citations

1. 6973605 - System and method for assured built in self repair of memories (2005-12-06),

2. 6966012 - Memory column redundancy circuitry and method for implementing the same (2005-11-15),

3. 6957402 - Yield maximization in the manufacture of integrated circuits (2005-10-18),

4. 6944582 - Methods for reducing bitline voltage offsets in memory devices (2005-09-13),

5. 6941525 - Leakage current reduction in standard cells (2005-09-06),

6. 6934213 - Method and apparatus for reducing write power consumption in random access memories (2005-08-23),

7. 6924687 - Voltage tolerant circuit for protecting an input buffer (2005-08-02),

8. 6915251 - Memories having reduced bitline voltage offsets (2005-07-05),

9. 6865119 - Negatively charged wordline for reduced subthreshold current (2005-03-08),

10. 6862721 - Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions (2005-03-01),

11. 6833624 - System and method for row decode in a multiport memory (2004-12-21),

12. 6788615 - System and method for low area self-timing in memory devices (2004-09-07),

13. 6750712 - Method and apparatus for voltage clamping in feedback amplifiers using resistors (2004-06-15),

14. 6731135 - Low voltage differential signaling circuit with mid-point bias (2004-05-04),

15. 6696852 - Low-voltage differential I/O device (2004-02-24),

Company Overview

Artisan Components, Inc., based in Sunnyvale, California, specializes in the development of advanced memory devices. The company focuses on innovative technologies such as Built In Self Repair and Memory Column Redundancy, which enhance the reliability and performance of integrated circuits. Their expertise extends to critical areas including bitline voltage offsets, leakage current reduction, and voltage tolerant circuits, catering to the evolving demands of low voltage differential signaling and programmable ROM solutions.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

50 Patents

#99 in Sunnyvale, CA

#1,646 in California

#6,999 in US

#13,996 in the World

Sunnyvale, CA, United States of America

Artisan Components, Inc.

Forward Citations = 908

23 inventors:

Scott T Becker (32 out of 228 patents)

Dhrumil Gandhi (12 out of 24 patents)

Steve P Kornachuk (8 out of 8 patents)

4. Mark Templeton (4 out of 4 patents)

5. Daniel F LaBouve (3 out of 3 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Artisan Components, Inc.. Retrieved from https://idiyas.com/company/artisan-components

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…