The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2005

Filed:

May. 29, 2003
Applicant:

Dhrumil Gandhi, Cupertino, CA (US);

Inventor:

Dhrumil Gandhi, Cupertino, CA (US);

Assignee:

Artisan Components, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F017/50 ;
U.S. Cl.
CPC ...
Abstract

A method for reducing leakage currents in integrated circuits and the integrated circuits with reduced leakage currents that result from this method are disclosed. The present invention determines which transistors in a standard logic cell (also known as a standard cell) are not critical with respect to the ultimate speed of operation of the standard logic cell. After determining which transistors do not critically impact the speed of the standard logic cell's operation, these designated transistors are designed with either lengthened channels or their channels are implanted. Both circuit design techniques will increase the threshold voltage (V) of the transistors and thereby reduce their leakage current. Standard cells with high Vtransistors in their non-critical circuit pathways exhibit reduced leakage currents when compared with known logic cells.


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