Categories: Centurion Plus Utility Patents

Centurion+ Patent Holders as of December 26, 2023

Chad Paul Boudreaux

Principal Design Engineer at Ethicon Endo-Surgery – J&J.

Patent №: 11849944 (December 26, 2023) – Drivers for fastener cartridge assemblies having rotary drive screws. This surgical device features a rotary input screw in the end effector, which enhances its functionality. The end effector includes improvements such as a better closure system, firing mechanisms, staple cartridge alignment, multi-staple drivers, single-firing knives, and safety features. Additionally, some components are 3D-printed for efficiency and precision.

Johann Alsmeier

Sr Director at Western Digital Corporation.

Patent №: 11856765 (December 26, 2023) – Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same.

This patent describes a three-dimensional memory device that features an alternating stack of insulating and electrically conductive layers. The device incorporates memory opening fill structures and drain-select-level isolation structures, which utilize low-k dielectric materials or air gaps to enhance performance and reduce power consumption.

Ching-Wei Tsai

Mr. Tsai was born in Tao-Yuan, Taiwan, R.O.C. He received his B.S. and Ph.D. degrees from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1998 and 2003, respectively, both in electronics engineering.

In 2003, he joined the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, where he is currently with the Department of Exploratory Technology Development. His research interests include ultrathin gate dielectric reliability of MOSFETs and nonvolatile memory devices such as flash memories and FeRAMs.

Patent №: 11854940 (December 26, 2023) – Semiconductor device having self-aligned interconnect structure and method of making, which introduces a novel self-aligned interconnect structure (SIS) embedded in a semiconductor substrate. This invention offers improved interconnectivity and integration, enabling more efficient and compact semiconductor designs.

Patent №: 11855224 (December 26, 2023) – Leakage prevention structure and method. The patent semiconductor device features an anti-punch-through (APT) region on a substrate, multiple channel members, gate structures surrounding each channel member, source/drain components near the gate structures, and a diffusion retardation layer. This layer, made of semiconductor material, separates the source/drain components from the APT region and the channel members.

Patent №: 11855090 (December 26, 2023) – High performance MOSFETs having varying channel structures. This patent describes the fabrication of gate-all-around nano-sheet FETs with tunable performance, involving the use of multilayer nano-sheet stacks and a metal gate structure. Such innovations hold the potential to enhance the performance and functionality of future electronic devices.

Chih-Wei Lin

Chih-Wei Lin is a Technical Manager at the Manufacturing Technology Center, TSMC. He received a B.S. and M.S. in Chemical Engineering from National Tsing Hua University in 1994 and 1996, respectively.

He is the project leader for the optimization and automation of Litho job file recipe creation and implementation for TSMC 8-inch and 12-inch fabs.

Patent №: 11854789 (December 26, 2023) – Method for manufacturing gate structure with additional oxide layer. This method involves forming a sealing layer, spacer, interfacial layer, gate dielectric layer, capping oxide layer, work function metal layer, and gate electrode layer. The innovative approach contributes to the development of more advanced and efficient gate structures.

Patent №: 11855006 (December 26, 2023) – Memory device, package structure and fabricating method thereof. This patent describes a memory device composed of a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation, and a buffer cap. The device enables efficient stacking and encapsulation of memory dies, enhancing overall performance and reliability.

Bharat Prasad

Principal Technical Architect, Inventor, USAA.

Patent №: 11854011 (December 26, 2023) – Identity management framework, which describes techniques for utilizing a decentralized identity management system. This method involves granting access to a user and storing their identity information within the decentralized system. Furthermore, the patent outlines the inclusion of reputation information associated with the user’s identity, enabling other users to contribute, and utilize this reputation information during transactions.

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Tags: Bharat PrasadChad Paul BoudreauxChih-Wei LinChing-Wei TsaiGorden WagenerHyoungsuk JeonIDiyasJohann AlsmeierJunyi LiMuhammad Ali KazmiProlific inventorsRichard P HowarthTingfang JiUSPTO

2 years ago

Angelina Kushnarova

Angelina Kushnarova (Sverediuk) was born in Ukraine. She graduated from Ternopil Medical University with a specialization in Medicine and completed an internship in Radiology at Lviv University. She worked as a Radiologist, while also working as a web developer.