The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Oct. 19, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Larry Zhao, Niskayuna, NY (US);

Ming He, Saratoga Springs, NY (US);

Xunyuan Zhang, Albany, NY (US);

Sean Xuan Lin, Watervliet, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/47 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10W 20/035 (2026.01); H10W 20/047 (2026.01); H10W 20/076 (2026.01); H10W 20/425 (2026.01); H10W 20/47 (2026.01);
Abstract

An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).


Find Patent Forward Citations

Zhao, Larry. (2026). Semiconductor device having a self-forming barrier layer at via bottom (U.S. Patent No. RE50914). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/RE50914

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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