The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2011
Filed:
Feb. 14, 2010
Mark Ellsberry, Santa Clara, CA (US);
Charles E. Schmitz, Granada Hills, CA (US);
Chi She Chen, Walnut, CA (US);
Victor Allison, Huntington, TX (US);
Jon Schmidt, San Juan Capistrano, CA (US);
Mark Ellsberry, Santa Clara, CA (US);
Charles E. Schmitz, Granada Hills, CA (US);
Chi She Chen, Walnut, CA (US);
Victor Allison, Huntington, TX (US);
Jon Schmidt, San Juan Capistrano, CA (US);
Sanmina-SCI Corporation, San Jose, CA (US);
Abstract
On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.