The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2018
Filed:
Dec. 28, 2016
Invensas Corporation, San Jose, CA (US);
Min Tao, San Jose, CA (US);
Hoki Kim, Santa Clara, CA (US);
Ashok S. Prabhu, San Jose, CA (US);
Zhuowen Sun, Campbell, CA (US);
Wael Zohni, San Jose, CA (US);
Belgacem Haba, Saratoga, CA (US);
Invensas Corporation, San Jose, CA (US);
Abstract
Package-on-package ('PoP') devices with same level wafer-level packaged ('WLP') components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.