The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jul. 19, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert L. Sankman, Phoenix, AZ (US);

Daniel N. Sobieski, Phoenix, AZ (US);

Sri Ranga Sai Boyapati, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01); H01G 4/33 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/18 (2006.01); H05K 3/46 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H01G 4/33 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 1/162 (2013.01); H05K 1/185 (2013.01); H05K 3/0017 (2013.01); H05K 3/188 (2013.01); H05K 3/467 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H05K 3/4644 (2013.01); H05K 2201/10015 (2013.01);
Abstract

An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.


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