The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Jul. 20, 2017
Applicant:

Pakal Technologies, Llc, San Francisco, CA (US);

Inventors:

Richard A. Blanchard, Los Altos, CA (US);

Vladimir Rodov, Seattle, WA (US);

Hidenori Akiyama, Miyagi, JP;

Woytek Tworzydlo, Austin, TX (US);

Assignee:

Pakal Technologies LLC, San Francisco, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/47 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7396 (2013.01); H01L 27/0716 (2013.01); H01L 29/083 (2013.01); H01L 29/105 (2013.01); H01L 29/47 (2013.01); H01L 29/7813 (2013.01); H01L 29/7839 (2013.01);
Abstract

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.


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