The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Apr. 09, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Takaaki Tsunomura, Kanagawa, JP;

Yoshiki Yamamoto, Kanagawa, JP;

Masaaki Shinohara, Kanagawa, JP;

Toshiaki Iwamatsu, Kanagawa, JP;

Hidekazu Oda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 27/1207 (2013.01); H01L 29/66477 (2013.01); H01L 29/66628 (2013.01); H01L 29/66651 (2013.01); H01L 29/7834 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 29/41783 (2013.01);
Abstract

On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.


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