The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2018
Filed:
Jan. 14, 2015
Intel Corporation, Santa Clara, CA (US);
Marko Radosavljevic, Beaverton, OR (US);
Prashant Majhi, San Jose, CA (US);
Jack T. Kavalieros, Portland, OR (US);
Niti Goel, Portland, OR (US);
Wilman Tsai, Saratoga, CA (US);
Niloy Mukherjee, Portland, OR (US);
Yong Ju Lee, Sunnyvale, CA (US);
Gilbert Dewey, Hillsboro, OR (US);
Willy Rachmady, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.