The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Nov. 09, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen M. Cea, Hillsboro, OR (US);

Anand S. Murthy, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Daniel B. Aubertine, North Plains, OR (US);

Tahir Ghani, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Roza Kotlyar, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/76224 (2013.01); H01L 29/06 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.


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