The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Sep. 28, 2015
Applicant:

Csmc Technologies Fab1 Co., Ltd., Wuxi New District, Jiangsu, CN;

Inventors:

Feng Huang, Jiangsu, CN;

Guangtao Han, Jiangsu, CN;

Guipeng Sun, Jiangsu, CN;

Feng Lin, Jiangsu, CN;

Longjie Zhao, Jiangsu, CN;

Huatang Lin, Jiangsu, CN;

Bing Zhao, Jiangsu, CN;

Lixiang Liu, Jiangsu, CN;

Liangliang Ping, Jiangsu, CN;

Fengying Chen, Jiangsu, CN;

Assignee:

CSMC Technologies Fab2 Co., Ltd., Wuxi New District, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66325 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/02318 (2013.01); H01L 21/26513 (2013.01); H01L 21/31116 (2013.01); H01L 29/0653 (2013.01); H01L 29/408 (2013.01); H01L 29/7393 (2013.01);
Abstract

The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (), an STI (), and a first N well ()/a first P well () which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well () of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (); performing photoetching and ion implantation so as to form a second N well () inside the first N well () and second P wells () inside the first N well () and the first P well (); then successively forming a gate oxide layer and a polysilicon gate (), wherein one end of the gate oxide layer and the polysilicon gate () extends onto the second P well () inside the first N well (), and the other end extends onto the mini oxide layer () on the second N well (); and photoetching and injecting N-type ions between the mini oxide layer () and the STI () adjacent to the mini oxide layer () to form a drain electrode, and at the same time forming a source electrode () inside the second P well ().


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