The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Jun. 25, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kyu-Oh Lee, Chandler, AZ (US);

Islam A. Salama, Scottsdale, AZ (US);

Ram S. Viswanath, Phoenix, AZ (US);

Robert L. Sankman, Phoenix, AZ (US);

Babak Sabi, Hillsboro, OR (US);

Sri Chaitra Jyotsna Chavali, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05147 (2013.01); H01L 2225/06517 (2013.01);
Abstract

Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.


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