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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9837396 B1

PDFFull Text
Date of Patent:
Dec. 05, 2017

Filed:

Sep. 01, 2016

Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Sameer S. Vadhavkar, Boise, ID (US);

Xiao Li, Boise, ID (US);

Steven K. Groothuis, Boise, ID (US);

Jian Li, Boise, ID (US);

Jaspreet S. Gandhi, Boise, ID (US);

James M. Derderian, Boise, ID (US);

David R. Hembree, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Perkins Coie LLP

Primary Examiner:

Victor A Mandala

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 25/16 (2006.01); H01L 21/56 (2006.01); H01L 23/04 (2006.01); H01L 21/50 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/4882 (2013.01); H01L 21/50 (2013.01); H01L 21/563 (2013.01); H01L 23/04 (2013.01); H01L 23/36 (2013.01); H01L 23/3675 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 25/167 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

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