The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2017

Filed:

Mar. 22, 2017
Applicant:

Phoenix Pioneer Technology Co., Ltd., Hsinchu County, TW;

Inventors:

Chu-Chin Hu, Hsinchu County, TW;

Shih-Ping Hsu, Hsinchu County, TW;

Che-Wei Hsu, Hsinchu County, TW;

Chin-Ming Liu, Hsinchu County, TW;

Chih-Kuai Yang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4832 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 21/563 (2013.01); H01L 21/566 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/5389 (2013.01); H01L 24/81 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/08238 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81192 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01);
Abstract

This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.


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