The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2017
Filed:
Nov. 16, 2016
United Microelectronics Corp., Hsin-Chu, TW;
Chao-Hung Lin, Changhua County, TW;
Chih-Kai Hsu, Tainan, TW;
Li-Wei Feng, Kaohsiung, TW;
Shih-Hung Tsai, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Jyh-Shyang Jenq, Pingtung County, TW;
Ching-Wen Hung, Tainan, TW;
Jia-Rong Wu, Kaohsiung, TW;
Yi-Hui Lee, Taipei, TW;
Ying-Cheng Liu, Tainan, TW;
Yi-Kuan Wu, Kaohsiung, TW;
Chih-Sen Huang, Tainan, TW;
Yi-Wei Chen, Taichung, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.