The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Jan. 05, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Chu Lin, Tainan, TW;

Hung-Che Liao, Tainan, TW;

Kun-Tsang Chuang, Miaoli County, TW;

Shih-Lu Hsu, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 29/0649 (2013.01); H01L 29/42324 (2013.01); H01L 29/42372 (2013.01); H01L 29/4916 (2013.01); H01L 29/788 (2013.01);
Abstract

A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.


Find Patent Forward Citations

Loading…