The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2017
Filed:
Dec. 31, 2014
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Kai-Shiang Kuo, Hsinchu, TW;
Ken-Yu Chang, Hsinchu, TW;
Ya-Lien Lee, Baoshan Township, TW;
Hung-Wen Su, Jhubei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/768 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76846 (2013.01); H01L 21/76867 (2013.01); H01L 21/76877 (2013.01); H01L 23/53223 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01); H01L 21/2855 (2013.01); H01L 21/28562 (2013.01); H01L 2924/0002 (2013.01);
Abstract
In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.