The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2017
Filed:
Jun. 10, 2016
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries Inc., Grand Cayman, KY;
Stmicroelectronics, Inc., Coppell, TX (US);
Qing Liu, Watervliet, NY (US);
Ruilong Xie, Schenectady, NY (US);
Chun-Chen Yeh, Clifton Park, NY (US);
Xiuyu Cai, Niskayuna, NY (US);
William J. Taylor, Clifton Park, NY (US);
International Business Machines Corporation, Armonk, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
STMICROELECTRONICS, INC., Coppell, TX (US);
Abstract
An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.