The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2017
Filed:
May. 13, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Shin-Puu Jeng, Hsin-Chu, TW;
Shang-Yun Hou, Jubei, TW;
Kim Hong Chen, Fremont, CA (US);
Wensen Hung, Zhubei, TW;
Szu-Po Huang, Taichung, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 21/683 (2006.01); H01L 25/18 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01); H01L 23/42 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/6835 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/367 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/3677 (2013.01); H01L 23/42 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68331 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/11003 (2013.01); H01L 2224/1111 (2013.01); H01L 2224/1183 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11848 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81805 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/157 (2013.01); H01L 2924/1532 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15159 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/2075 (2013.01); H01L 2924/20751 (2013.01); H01L 2924/20752 (2013.01); H01L 2924/20753 (2013.01); H01L 2924/20754 (2013.01); H01L 2924/20755 (2013.01);
Abstract
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.