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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9780009 B1

PDFFull Text
Date of Patent:
Oct. 03, 2017

Filed:

Nov. 23, 2015

Integrated circuit packages and methods for forming the same

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chia-Wei Tu, Hsin-Chu, TW;

Hsien-Wei Chen, Hsin-Chu, TW;

Tsung-Fu Tsai, Hsin-Chu, TW;

Wen-Hsiung Lu, Hsin-Chu, TW;

Yian-Liang Kuo, Hsin-Chu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Caleb Henry

Assistant Examiner:

Mounir Amer

Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/58 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 21/78 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/15 (2013.01); H01L 23/3107 (2013.01); H01L 23/3157 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0502 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05099 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/94 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/14 (2013.01);
Abstract

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Find Patent Forward Citations

Tu, Chia-Wei. (2017). Integrated circuit packages and methods for forming the same (U.S. Patent No. 9780009). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9780009

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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