The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Jul. 20, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yung-Yao Lee, Zhubei, TW;

Heng-Hsin Liu, New Taipei, TW;

Yi-Ping Hsieh, Hsinchu, TW;

Ying Ying Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); G03F 7/20 (2006.01); H01L 21/66 (2006.01); G06F 17/50 (2006.01); G01N 21/95 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70633 (2013.01); G03F 9/7003 (2013.01); G06F 17/5081 (2013.01); H01L 22/20 (2013.01); G01N 21/9501 (2013.01); H01L 22/12 (2013.01);
Abstract

An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.


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