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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9768269 B1

PDFFull Text
Date of Patent:
Sep. 19, 2017

Filed:

Sep. 18, 2014

Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert Dewey, Hillsboro, OR (US);

Niloy Mukherjee, Portland, OR (US);

Matthew Metz, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Nancy M. Zelick, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt P.C.

Primary Examiner:

Teresa M Arroyo

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/31 (2006.01); H01L 21/469 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01); H01L 23/52 (2006.01); H01L 29/51 (2006.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 51/52 (2006.01); H01L 31/0224 (2006.01); H01L 21/04 (2006.01); H01L 51/10 (2006.01); H01L 51/44 (2006.01); H01L 29/45 (2006.01); H01L 45/00 (2006.01); H01L 33/00 (2010.01); H01B 1/12 (2006.01); H01L 33/40 (2010.01);
U.S. Cl.
CPC ...
H01L 29/517 (2013.01); H01L 21/28525 (2013.01); H01L 21/324 (2013.01); H01L 21/76831 (2013.01); H01L 21/76841 (2013.01); H01L 23/485 (2013.01); H01L 23/53223 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01); H01L 29/4966 (2013.01); H01L 29/512 (2013.01); H01L 29/66643 (2013.01); H01L 29/7839 (2013.01); H01L 29/7853 (2013.01); H01B 1/122 (2013.01); H01L 21/048 (2013.01); H01L 21/76834 (2013.01); H01L 29/45 (2013.01); H01L 29/518 (2013.01); H01L 31/022466 (2013.01); H01L 31/022475 (2013.01); H01L 33/0041 (2013.01); H01L 33/40 (2013.01); H01L 45/08 (2013.01); H01L 45/1206 (2013.01); H01L 45/1253 (2013.01); H01L 45/1266 (2013.01); H01L 45/145 (2013.01); H01L 51/102 (2013.01); H01L 51/105 (2013.01); H01L 51/441 (2013.01); H01L 51/442 (2013.01); H01L 51/5203 (2013.01); H01L 51/5234 (2013.01); H01L 2251/301 (2013.01); H01L 2251/303 (2013.01); H01L 2251/306 (2013.01); H01L 2251/308 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

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