The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jun. 14, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Justin K. Brask, Portland, OR (US);

Jack Kavalieros, Portland, OR (US);

Brian S. Doyle, Portland, OR (US);

Uday Shah, Portland, OR (US);

Suman Datta, Beaverton, OR (US);

Amlan Majumdar, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 21/84 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 21/3085 (2013.01); H01L 21/30608 (2013.01); H01L 21/30617 (2013.01); H01L 21/84 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/0657 (2013.01); H01L 29/51 (2013.01); H01L 29/66795 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01);
Abstract

A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.


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