The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Sep. 12, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Dominic Thurmer, Dresden, DE;

Hans-Juergen Thees, Dresden, DE;

Kai Frohberg, Niederau, DE;

Peter Moll, Dresden, DE;

Heike Scholz, Hirschfeld, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6653 (2013.01); H01L 21/31105 (2013.01); H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 21/32132 (2013.01); H01L 29/42376 (2013.01);
Abstract

The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.


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