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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9754925 B1

PDFFull Text
Date of Patent:
Sep. 05, 2017

Filed:

Aug. 08, 2016

3dic interconnect apparatus and method

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shu-Ting Tsai, Kaohsiung, TW;

Dun-Nian Yaung, Taipei, TW;

Jen-Cheng Liu, Hsin-Chu, TW;

U-Ting Chen, Wanluan Township, TW;

Shih-Pei Chou, Tainan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Sitaramarao S Yechuri

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/24 (2013.01); H01L 24/80 (2013.01); H01L 24/82 (2013.01); H01L 24/91 (2013.01); H01L 25/50 (2013.01); H01L 21/76805 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/821 (2013.01); H01L 2224/82031 (2013.01); H01L 2224/92 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/9212 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/12036 (2013.01);
Abstract

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

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