The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Jul. 13, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Ding Wang, Tainan, TW;

Bo-I Lee, Sindian, TW;

Chien-Hsun Lee, Chu-Tung Town, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); B32B 37/02 (2006.01); B32B 38/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/97 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/67005 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); B32B 37/02 (2013.01); B32B 38/0004 (2013.01); B32B 2457/14 (2013.01); H01L 21/67144 (2013.01); H01L 24/16 (2013.01); H01L 2224/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01);
Abstract

A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.


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