The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2017
Filed:
Aug. 29, 2016
Applicant:
Pfg Ip Llc, Tiburon, CA (US);
Inventors:
Randy Bindrup, Costa Mesa, CA (US);
W. Eric Boyd, Costa Mesa, CA (US);
John Leon, Costa Mesa, CA (US);
James Yamaguchi, Costa Mesa, CA (US);
Assignee:
PFG IP LLC, Tiburon, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/45 (2013.01); H01L 23/498 (2013.01); H01L 23/49811 (2013.01); H01L 24/05 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/45541 (2013.01);
Abstract
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond 'through-via' accessible from at least the lower or second surface of the layer.