The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Jul. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Ru Lee, Hsinchu, TW;

Ming-Hua Yu, Hsinchu, TW;

Tze-Liang Lee, Hsinchu, TW;

Chii-Horng Li, Jhu-Bei, TW;

Pang-Yen Tsai, Jhu-Bei, TW;

Lilly Su, Chu-Bei, TW;

Yi-Hung Lin, Taipei, TW;

Yu-Hung Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/306 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02661 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/30604 (2013.01); H01L 21/30608 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823425 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 29/045 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/66636 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.


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