The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Feb. 16, 2012
Louis W. Nicholls, Gilbert, AZ (US);
Roger D. St. Amand, Tempe, AZ (US);
Jin Seong Kim, Seoul, KR;
Woon Kab Jung, Seoul, KR;
Sung Jin Yang, Seoul, KR;
Robert F. Darveaux, Gilbert, AZ (US);
Louis W. Nicholls, Gilbert, AZ (US);
Roger D. St. Amand, Tempe, AZ (US);
Jin Seong Kim, Seoul, KR;
Woon Kab Jung, Seoul, KR;
Sung Jin Yang, Seoul, KR;
Robert F. Darveaux, Gilbert, AZ (US);
AMKOR TECHNOLOGY, INC., Tempe, AZ (US);
Abstract
A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.