The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2017
Filed:
Aug. 18, 2011
Jen-chi Chang, Hsinchu, TW;
Chun-li Lin, Hsinchu, TW;
Kai-shiung Hsu, Kaohsiung, TW;
Ming-shiou Kuo, Taichung, TW;
Wen-long Lee, Hsinchu, TW;
Po-hsiung Leu, Lujhu Township, Taoyuan County, TW;
Ding-i Liu, Hsinchu, TW;
Jen-Chi Chang, Hsinchu, TW;
Chun-Li Lin, Hsinchu, TW;
Kai-Shiung Hsu, Kaohsiung, TW;
Ming-Shiou Kuo, Taichung, TW;
Wen-Long Lee, Hsinchu, TW;
Po-Hsiung Leu, Lujhu Township, Taoyuan County, TW;
Ding-I Liu, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Abstract
The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.