The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2017
Filed:
Aug. 19, 2014
Manohar S. Konchady, Chandler, AZ (US);
Tao Wu, Chandler, AZ (US);
Mihir K. Roy, Chandler, AZ (US);
Wei-lun K. Jen, Chandler, AZ (US);
Yi LI, Chandler, AZ (US);
Manohar S. Konchady, Chandler, AZ (US);
Tao Wu, Chandler, AZ (US);
Mihir K. Roy, Chandler, AZ (US);
Wei-Lun K. Jen, Chandler, AZ (US);
Yi Li, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.