The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Feb. 02, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Hang Tung, Hsin-Chu, TW;

Chun Hui Yu, Zhubei, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Da-Yuan Shih, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/4882 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/76879 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/27 (2013.01); H01L 24/33 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73217 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/8203 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01029 (2013.01);
Abstract

A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.


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