The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jul. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kevin K. Chan, Staten Island, NY (US);

Marinus J. P. Hopstaken, Carmel, NY (US);

Young-Hee Kim, Mohegan Lake, NY (US);

Masaharu Kobayashi, Tokyo, JP;

Effendi Leobandung, Stormville, NY (US);

Deborah A. Neumayer, Danbury, CT (US);

Dae-Gyu Park, Poughquag, NY (US);

Uzma Rana, Chappaqua, NY (US);

Tsong-Lin Tai, Stormville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 29/66 (2006.01); H01L 21/24 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 21/322 (2006.01); H01L 21/324 (2006.01); H01L 29/267 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/242 (2013.01); H01L 21/2257 (2013.01); H01L 21/2258 (2013.01); H01L 21/28575 (2013.01); H01L 21/3228 (2013.01); H01L 21/3245 (2013.01); H01L 29/267 (2013.01); H01L 29/452 (2013.01); H01L 29/665 (2013.01); H01L 29/66522 (2013.01); H01L 29/517 (2013.01);
Abstract

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.


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