The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
May. 17, 2016
Globalfoundries Inc., Grand Cayman, KY;
Stmicroelectronics, Inc., Coppell, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Ajey Poovannummoottil Jacob, Watervliet, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce Doris, Slingerlands, NY (US);
Nicolas Loubet, Guilderland, NY (US);
Prasanna Khare, Schenectady, NY (US);
Rama Divakaruni, Ossining, NY (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
STMicroelectronics, Inc., Coppel;l, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.