The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Apr. 09, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chuan Hu, Chandler, AZ (US);

Qing Ma, Saratoga, CA (US);

Chia-Pin Chiu, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 25/0652 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92133 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/18162 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.


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