The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Apr. 11, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Tuhin Guha Neogi, Clifton Park, NY (US);

David Pritchard, Glenville, NY (US);

Scott Luning, Albany, NY (US);

Guillaume Bouche, Albany, NY (US);

David Doman, Austin, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 21/285 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/28518 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/7838 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.


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