The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9658538 B1

PDF
Full Text
Expired
Date of Patent:
May. 23, 2017

Filed:

Dec. 19, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Pei-Yi Liu, Changhua, TW;

Cheng-Chi Wu, Hsinchu, TW;

Cheng-Hung Chen, Zhubei, TW;

Jyuh-Fuh Lin, Chunan Township, TW;

Wen-Chuan Wang, Hsinchu, TW;

Shy-Jay Lin, Jhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70508 (2013.01); G03F 7/70291 (2013.01); G03F 7/70383 (2013.01); H01J 2237/31764 (2013.01);
Abstract

A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.


Find Patent Forward Citations

Liu, Pei-Yi. (2017). System and technique for rasterizing circuit layout data (U.S. Patent No. 9658538). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9658538

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