The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Apr. 24, 2012
Chang-shen LU, New Taipei, TW;
Chih-tang Peng, Taipei, TW;
Tai-chun Huang, Hsin-Chu, TW;
Pei-ren Jeng, Chu-Bei, TW;
Hao-ming Lien, Hsin-Chu, TW;
Yi-hung Lin, Taipei, TW;
Tze-liang Lee, Hsin-Chu, TW;
Syun-ming Jang, Hsin-Chu, TW;
Chang-Shen Lu, New Taipei, TW;
Chih-Tang Peng, Taipei, TW;
Tai-Chun Huang, Hsin-Chu, TW;
Pei-Ren Jeng, Chu-Bei, TW;
Hao-Ming Lien, Hsin-Chu, TW;
Yi-Hung Lin, Taipei, TW;
Tze-Liang Lee, Hsin-Chu, TW;
Syun-Ming Jang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.