The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jan. 24, 2014
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Xiuyu Cai, Niskayuna, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Johnathan E. Faltermeier, Delanson, NY (US);

Ali Khakifirooz, Mountain View, CA (US);

Theodorus E. Standaert, Clifton Park, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 21/84 (2006.01); H01L 21/311 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/31111 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/845 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/665 (2013.01);
Abstract

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.


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