The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Dec. 30, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsunchu, TW;

Inventors:

Chun-wen Cheng, Zhubei, TW;

Jung-Huei Peng, Jhubei, TW;

Shang-Ying Tsai, Pingzhen, TW;

Hung-Chia Tsai, Taichung, TW;

Yi-Chuan Teng, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); B81B 7/00 (2006.01); B81B 7/04 (2006.01); B81C 1/00 (2006.01); B81B 7/02 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81B 7/02 (2013.01); B81B 7/04 (2013.01); B81C 1/0023 (2013.01); B81C 1/00214 (2013.01); B81C 1/00333 (2013.01);
Abstract

A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.


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