The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Sep. 25, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Kian Meng Heng, Singapore, SG;

Hin Hwa Goh, Singapore, SG;

Jose Alvin Caparas, Singapore, SG;

Kang Chen, Singapore, SG;

Seng Guan Chow, Singapore, SG;

Yaojian Lin, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 24/19 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.


Find Patent Forward Citations

Loading…