The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Oct. 23, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Jongsun Sel, Los Gatos, CA (US);

Chan Park, Mountain View, CA (US);

Atsushi Suyama, San Jose, CA (US);

Frank Yu, Cupertino, CA (US);

Hiroyuki Ogawa, Nagoya, JP;

Ryoichi Honma, Yokkaichi, JP;

Kensuke Yamaguchi, Yokkaichi, JP;

Hiroaki Iuchi, Nagoya, JP;

Naoki Takeguchi, Yokkaichi, JP;

Tuan Pham, San Jose, CA (US);

Kiyohiko Sakakibara, Yokkaichi, JP;

Jiao Chen, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11578 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/7883 (2013.01);
Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.


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