The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Aug. 28, 2014
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Ze-Ming Wu, Tainan, TW;
Shih Hsin Chen, Hsinchu, TW;
Chien-Chih Kuo, Hsinchu, TW;
Kai-Ming Liu, Hsinchu, TW;
Hsien-Hsin Sean Lee, Duluth, GA (US);
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Abstract
One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.